IMX7DCEC datasheet(68/161 Pages) NXP

tên linh kiện	IMX7DCEC

Giải thích chi tiết về linh kiện	i.MX 7Dual Family of Applications Processors Datasheet

PDF	161 Pages

Scroll/Zoom	100%

nhà sản xuất	NXP [NXP Semiconductors]

Trang chủ	http://www.nxp.com

Logo

68 / 161 page

Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

Figure 26 shows the DDR3 read timing diagram. The timing parameters for this diagram appear in

Table 49.

Figure 26. DDR3 read cycle

1 To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P

in the middle of DRAM_DATAxx window.

2 All measurements are in reference to Vref level.

3 Measurements were done using balanced load and 25  resistor from outputs to VDD_REF.

4.8.4.2

LPDDR3 parameters

Figure 27 shows the LPDDR3 basic timing diagram. The timing parameters for this diagram appear in

Table 50.

Figure 27. LPDDR3 command and address timing diagram

Table 49. DDR3 read cycle

Parameter

Symbol

CK = 533 MHz

Unit

Min

Max

DDR26

Minimum required DRAM_DATAxx valid window width

—

510

—

DRAM_SDCLKx_P

DRAM_SDCLKx_N

DRAM_SDQSx_P

DRAM_DATAxx

DATA

DDR26

(input)

IMX7DCEC bảng dữ liệu(PDF) 68 Page - NXP Semiconductors