IMX7DCEC datasheet(91/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

4.10.3.1.3 MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)

Figure 53 shows MII asynchronous input timings. Table 68 describes the timing parameter (M9) shown in

the figure.

Figure 53. MII async inputs timing diagram

1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

4.10.3.1.4 MII Serial management channel timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3

MII specification. However the ENET can function correctly with a maximum MDC frequency of

15 MHz.

Figure 54 shows MII asynchronous input timings. Table 69 describes the timing parameters (M10–M15)

shown in the figure.

Figure 54. MII serial management channel timing diagram

Table 68. MII asynchronous inputs signal timing

Characteristic

Min.

Max.

Unit

M91

ENET_CRS to ENET_COL minimum pulse width

1.5

—

ENET_TX_CLK period

ENET_CRS, ENET_COL

ENET_MDC (output)

ENET_MDIO (output)

M14

M15

M10

M11

M12 M13

ENET_MDIO (input)

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