IMX7DCEC datasheet(96/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

4.10.6 LCD controller (LCDIF) timing parameters

Figure 60 shows the LCDIF timing and Table yy lists the timing parameters.

Figure 60. LCD timing

4.10.7 Parallel CMOS sensor interface (CSI) timing parameters

4.10.7.1 Gated clock mode timing

Figure 61 and Figure 62 shows the gated clock mode timings for CSI, and Table 74 describes the timing

parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC

Table 73. LCD timing parameters

Parameter

Symbol

Min Max Unit

LCD pixel clock frequency

tCLK(LCD)

150 MHz

LCD pixel clock high (falling edge capture)

tCLKH(LCD)

LCD pixel clock low (rising edge capture)

tCLKL(LCD)

LCD pixel clock high to data valid (falling edge capture)

td(CLKH-DV)

-1

LCD pixel clock low to data valid (rising edge capture)

td(CLKL-DV)

-1

LCD pixel clock high to control signals valid (falling edge capture)

td(CLKH-CTRLV)

-1

LCD pixel clock low to control signals valid (rising edge capture)

td(CLKL-CTRLV)

-1

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