IMX7DCEC datasheet(8/161 Pages) NXP

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Architectural overview

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

Architectural overview

The following subsections provide an architectural overview of the i.MX 7Dual processor system.

2.1

Block diagram

Figure 2 shows the functional modules in the i.MX 7Dual processor system.

Figure 2. i.MX 7Dual System block diagram

Debug

DAP

TPIU

CTIs

SJC

Shared Peripherals

Internal Memory

OCRAM 320KB

ROM 96KB

External Memory

DDR Controller

EIM

SPBA

PLLs

CCM

GPC

SRC

XTAL OSC

RC OSC

Timers

System Counter

Camera Interface

CSI

EPD Controller

Image Processing

Security

CSU

OCOTP (eFuse)

Power Management

LDOs

AP Peripherals

KPP

Sensors

Modem IC

EPD Panel

PCIe Bus

Camera

LCD Panel

Tamper

Detection

Keypad

WLAN

Touch Panel

Control

GPMI&BCH

QSPI

MPU

FPU

NAND FLASH

Display Interface

LCDIF

MIPI DSI

Smart DMA

SDMA

RDC

SEMAPHORE

NEON

FPU

Temp Monitor

IOMUX

ADC (2)

LPDDR2/LPDDR3

Battery Ctrl

Device

JTAG

(IEEE1149.6)

Crystal&

Clock Source

NOR Flash

(Parallel)

CAAM

(32KB RAM)

SNVS(SRTC)

NOR FLASH

(Quad SPI)

MIPI CSI(2 lane)

USB OTG

(dev/host)

CAN x2

Pixel Processing

Pipeline(PXP)

Multi-Core Unit

TCM 64KB

I$ 16KB

D$ 16KB

Cortex-M4 Core

ARM Cortex M4

Platform

L2 Cache 512KB

SCU & Timer

I$ 32KB D$ 32KB

CPU0

CPU1

ARM Cortex A7

MPCore Platform

WDOG(4)

GPT(4)

Flex Timer(2)

eCSPI(3)

SAI(3)

UART(3)

GPIO(7)

UART(4)

PWM(4)

eCSPI(1)

I2C(4)

SIMv2(2)

FlexCAN(2)

PCIe v2.1

AVB ENET(2)

uSDHC(3)

Clock & Reset

10/100/1000M

Ethernet x2

MMC/SD

eMMC/eSD

MMC/SD

SDXC

/DDR3/DDR3L

Smart Card x2

OCOTP

Host (1) / OTG (2)

USB 2.0

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