IMX7DCEC datasheet(5/161 Pages) NXP

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i.MX 7Dual introduction

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

— 32 KByte L1 Instruction Cache

— 32 KByte L1 Data Cache

— Private Timer and Watchdog

— NEON MPE (media processing engine) coprocessor

The Arm Cortex-A7 Core complex shares:

• General interrupt controller (GIC) with 128 interrupt support

• Global timer

• Snoop control unit (SCU)

• 512 KB unified I/D L2 cache

• Two master AXI bus interfaces output of L2 cache

• Frequency of the core (including NEON and L1 cache), as per Table 9.

• NEON MPE coprocessor

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

The Arm Cortex-M4 platform:

• Cortex-M4 CPU core

• MPU (memory protection unit)

• FPU (floating-point unit)

• 16 KByte instruction cache

• 16 KByte data cache

• 64 KByte TCM (tightly-coupled memory)

The SoC-level memory system consists of the following additional components:

— Boot ROM, including HAB (96 KB)

— Internal multimedia / shared, fast access RAM (256 KB of total OCRAM)

— Secure/nonsecure RAM (32 KB)

• External memory interfaces: The i.MX 7Dual family of processors supports the latest,

high-volume, cost effective DRAM, NOR, and NAND Flash memory standards.

— Up to 32-bit LP-DDR2-1066, DDR3-1066, DDR3L-1066, and LPDDR3-1066

— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,

BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 62 bits.

— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.

Each i.MX 7Dual processor enables the following interfaces to external devices (some of them are muxed

and not available simultaneously):

• Displays—Available interfaces.

IMX7DCEC bảng dữ liệu(PDF) 5 Page - NXP Semiconductors