IMX7DCEC datasheet(109/161 Pages) NXP

109 / 161 page

Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

109

• For loopback DQS sampling, the data strobe is output to the DQS pad

together with the serial clock. The data strobe is looped back from DQS

pad and used to sample input data.

Figure 76. QuadSPI Output/Write Timing (DDR mode)

NOTE

Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the default

value of 3 are shown on the timing. See the i.MX 7Dual Reference Manual

(IMX7DRM) for more details.

4.10.12 SAI/I2S switching specifications

This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.

All timings are given for noninverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] =

0) and noninverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock

and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal

(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

Table 84. QuadSPI Output/Write Timing (DDR mode)

Symbol

Parameter

Value

Unit

Min

Max

TDVO

Output data valid time

—

(0.25 x TSCLK) + 2.5 ns

TDHO

Output data hold time

(0.25 x TSCLK) - 0.5

—

TCK

SCK clock period

—

TCSS

Chip select output setup time

—

SCK cycle(s)

TCSH

Chip select output hold time

—

SCK cycle(s)

Table 85. Master mode SAI timing

Num

Characteristic

Min

Max

Unit

SAI_MCLK cycle time

—

SAI_MCLK pulse width high/low

40%

60%

MCLK period

SAI_BCLK cycle time

—

SAI_BCLK pulse width high/low

40%

60%

BCLK period

TCSS

TCK

TDVO

TDHO

TDVO

TDHO

TCSH

QSPIx_SCLK

QSPIx_CS

QSPIx_SIO

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