CC1110-RTY1 datasheet(143/203 Pages) TI

143 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 143 of 202

U0GCR (0xC5) – USART 0 Generic Control

Bit

Name

Reset

R/W

Description

SPI clock polarity

Negative clock polarity

CPOL

R/W

Positive clock polarity

SPI clock phase

Data is output on MOSI when SCK goes from

CPOL inverted

CPOL, and data input is sampled on MISO when SCK goes

from

CPOL to CPOL inverted.

CPHA

R/W

Data is output on MOSI when SCK goes from

CPOL to CPOL

inverted, and data input is sampled on MISO when SCK goes

from

CPOL inverted to CPOL.

Bit order for transfers

LSB first

ORDER

R/W

MSB first

4:0

BAUD_E[4:0]

0x00

R/W

Baud rate exponent value.

BAUD_E along with BAUD_M decides

the UART baud rate and the SPI master SCK clock frequency

U0DBUF (0xC1) – USART 0 Receive/Transmit Data Buffer

Bit

Name

Reset

R/W

Description

7:0

DATA[7:0]

0x00

R/W

USART receive and transmit data. When writing this register the

data written is written to the internal transmit data register. When

reading this register, the data from the internal read data register is

read.

U0BAUD (0xC2) – USART 0 Baud Rate Control

Bit

Name

Reset

R/W

Description

7:0

BAUD_M[7:0]

0x00

R/W

Baud rate mantissa value.

BAUD_E along with BAUD_M decides

the UART baud rate and the SPI master SCK clock frequency

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