CC1110-RTY1 datasheet(27/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 27 of 202

time counter that runs regardless of operating

mode (except power mode 3) or as a wakeup

timer to get out of power modes 1 or 2. See

section 13.5 for details.

A built-in watchdog timer allows the

CC1110 to

reset itself in case the firmware hangs. When

enabled, the watchdog timer must be cleared

periodically, otherwise it will reset the device

when it times out. See section 13.12 for

details.

Timer

16-bit

timer

with

timer/counter/PWM functionality. It has a

programmable prescaler, a 16-bit period value

and

three

individually

programmable

counter/capture channels each with a 16-bit

compare value. Each of the counter/capture

channels can be used as PWM outputs or to

capture the timing of edges on input signals.

See section 13.3 for details.

Timer 2 (MAC timer) is specifically designed

to support time-slotted protocols in software.

The timer has a configurable timer period and

18-bit tunable prescaler range. See section

13.4 for details.

Timers 3 and 4 are 8-bit timers with

timer/counter/PWM functionality. They have a

programmable prescaler, an 8-bit period value

and

one

programmable

counter/capture

channel with an 8-bit compare value. Each of

the counter/capture channels can be used as

PWM outputs or to capture the timing of edges

on input signals. See section 13.6 for details.

USART 0 and 1 are each configurable as

either an SPI master/slave or a UART. They

provide double buffering on both RX and TX

and hardware flow-control and are thus well

suited

high-throughput

full-duplex

applications. Each has its own high-precision

baud-rate generator thus leaving the ordinary

timers free for other uses. When configured as

an SPI slave they sample the input signal

using SCK directly instead of some over-

sampling scheme and are thus well suited to

high data rates. See section 13.13 for details.

The AES encryption/decryption core allows

the user to encrypt and decrypt data using the

AES algorithm with 128-bit keys. See section

13.9 for details.

The ADC supports 8 to 14 bits of resolution in

a 30 kHz to 4 kHz bandwidth respectively. DC

and audio conversion with up to eight input

channels (Port 0) is possible. The inputs can

be selected as single ended or differential.

The reference voltage can be internal, AVDD,

or a single ended or differential external signal.

The ADC also has a temperature sensor input

channel. The ADC can automate the process

of periodic sampling or conversion over a

sequence of channels. See Section 13.7 for

details.

9.2

Radio

CC1110 features an RF transceiver based on

the industry-leading

CC1100, requiring very few

external components. See Section 15 for

details.

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