ATAM862 datasheet(88/110 Pages) ATMEL

88 / 110 page

4554E–4BMCU–05/06

ATAM862-3

24.2.1

Combination Mode 6: FSK Modulation

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 8:

FSK modulation with shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data output

selects which compare register is used for the output frequency generation. A "0" level at the

SSI data output enables the compare register 1 and a "1" level enables the compare register 2.

The compare and compare mode registers must be programmed to generate the two frequen-

cies via the output toggle flip-lop. The SSI can be supplied with the toggle signal of Timer 2 or

any other clock source. The Timer 3 counter is driven by an internal or external clock source.

Figure 24-8. FSK Modulation

24.2.2

Combination Mode 7: Pulse-width Modulation (PWM)

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 9:

Pulse-width modulation with the shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data output

selects which compare register is used for the output pulse generation. In this mode, both com-

pare and compare mode registers must be programmed to generate the two pulse width. It is

also useful to enable the single-action mode for extreme duty cycles. Timer 2 is used as

baudrate generator and for the triggered restart of Timer 3. The SSI must be supplied with the

toggle signal of Timer 2. The counter is driven by an internal or external clock source.

Figure 24-9. Pulse-width Modulation

0 1 23 40 123 401 20

Counter 3

CM31

CM32

12 012 0120 12 01 2 0 12 01 20 1234 0

T3R

T3O

000 0 0 00 00

000 0

Counter 3

CM31

CM32

T3O

00 0 001 234 56 7 8 9 1011121314150 12 345

TOG2

67 8

91112

2 3

SIR

SCO

T3R

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