T89C51RC2-3CSIM datasheet(75/117 Pages) ATMEL

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T89C51RB2/RC2

4105D–8051–10/06

Power Management

Two power reduction modes are implemented in the T89C51RB2/RC2: the Idle mode

and the Power-Down mode. These modes are detailed in the following sections. In addi-

tion to these power reduction modes, the clocks of the core and peripherals can be

dynamically divided by 2 using the X2 mode detailed in Section “Clock”.

Reset

A reset is required after applying power at turn-on. To achieve a valid reset, the reset

signal must be maintained for at least 2 machine cycles (24 oscillator clock periods)

while the oscillator is running and stabilized and VCC established within the specified

operating ranges. A device reset initializes the T89C51RB2/RC2 and vectors the CPU

to address 0000h. RST input has a pull-down resistor allowing power-on reset by simply

connecting an external capacitor to VDD as shown in Figure 31. Resistor value and input

ch a r a c te ri sti cs a r e d i scu ss e d i n th e Se cti o n “ DC Ch a r a c te ri sti cs” o f th e

T89C51RB2/RC2 datasheet. The status of the Port pins during reset is detailed in

Table 53.

Figure 31. Reset Circuitry and Power-On Reset

Table 53. Pin Conditions in Special Operating Modes

Reset Recommendation

to Prevent Flash

Corruption

A bad reset sequence will lead to bad microcontroller initialization and system registers

like SFR’s, Program Counter, etc. will not be correctly initialized. A bad initialization may

lead to unpredictable behaviour of the C51 microcontroller.

An example of this situation may occur in an instance where the bit ENBOOT in AUXR1

ping of the bootloader in the code area, a reset failure can be critical.

If one wants the ENBOOT cleared inorder to unmap the boot from the code area (yet

due to a bad reset) the bit ENBOOT in SFR’s may be set. If the value of Program

Counter is accidently in the range of the boot memory addresses then a flash access

(write or erase) may corrupt the Flash on-chip memory .

It is recommended to use an external reset circuitry featuring power supply monitoring to

prevent system malfunction during periods of insufficient power supply voltage(power

supply failure, power supply switched off).

Mode

Port 0

Port 1

Port 2

Port 3

Port 4

ALE

PSEN#

Reset

Floating

High

Idle

Data

High

Power-

Down

Data

Low

RST

VSS

To CPU core

and peripherals

RST

VDD

b. Power-on Reset

a. RST input circuitry

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