MC908QT4MPE datasheet(104/184 Pages) FREESCALE

104 / 184 page

System Integration Module (SIM)

MC68HC908QY/QT Family Data Sheet, Rev. 5

104

Freescale Semiconductor

Figure 13-1. SIM Block Diagram

13.2 RST and IRQ Pins Initialization

RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be

activated by programing CONFIG2 accordingly. Refer to Chapter 5 Configuration Register (CONFIG).

13.3 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The

system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 13-2.

STOP/WAIT

CLOCK

CONTROL

CLOCK GENERATORS

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

INTERRUPT CONTROL

AND PRIORITY DECODE

MODULE STOP

MODULE WAIT

CPU STOP (FROM CPU)

CPU WAIT (FROM CPU)

SIMOSCEN (TO OSCILLATOR)

BUSCLKX2 (FROM OSCILLATOR)

INTERNAL CLOCKS

MASTER

RESET

CONTROL

RESET

PIN LOGIC

ILLEGAL OPCODE (FROM CPU)

ILLEGAL ADDRESS (FROM ADDRESS

MAP DECODERS)

COP TIMEOUT (FROM COP MODULE)

INTERRUPT SOURCES

CPU INTERFACE

RESET

CONTROL

SIM

COUNTER

COP CLOCK

BUSCLKX4 (FROM OSCILLATOR)

÷2

LVI RESET (FROM LVI MODULE)

VDD

INTERNAL

PULL-UP

FORCED MON MODE ENTRY (FROM MENRST MODULE)

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