MC908QT4MPE datasheet(99/184 Pages) FREESCALE

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Port A

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

Figure 12-3 shows the port A I/O logic.

Figure 12-3. Port A I/O Circuit

NOTE

Figure 12-3 does not apply to PTA2

When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading

address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the

state of its data direction bit.

12.2.3 Port A Input Pullup Enable Register

The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each

if the six port A pins. Each bit is individually configurable and requires the corresponding data direction

when its corresponding DDRAx bit is configured as output.

OSC2EN — Enable PTA4 on OSC2 Pin

This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is

selected. This bit has no effect for the XTAL or external oscillator options.

1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4)

0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions

Address: $000B

Bit 7

654321

Bit 0

Read:

OSC2EN

PTAPUE5

PTAPUE4

PTAPUE3

PTAPUE2

PTAPUE1

PTAPUE0

Write:

Reset:

00000000

= Unimplemented

Figure 12-4. Port A Input Pullup Enable Register (PTAPUE)

READ DDRA ($0004)

WRITE DDRA ($0004)

RESET

WRITE PTA ($0000)

READ PTA ($0000)

PTAx

DDRAx

PTAx

30 k

PTAPUEx

TO KEYBOARD INTERRUPT CIRCUIT

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