MC908QT4MPE datasheet(101/184 Pages) FREESCALE

101 / 184 page

Port B

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

101

12.3.2 Data Direction Register B

Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1

to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.

DDRB[7:0] — Data Direction Register B Bits

These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins

as inputs.

1 = Corresponding port B pin configured as output

0 = Corresponding port B pin configured as input

NOTE

Avoid glitches on port B pins by writing to the port B data register before

changing data direction register B bits from 0 to 1. Figure 12-7 shows the

port B I/O logic.

Figure 12-7. Port B I/O Circuit

When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading

address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the

state of its data direction bit. Table 12-2 summarizes the operation of the port B pins.

Address: $0005

Bit 7

Bit 0

Read:

DDRB7

DDRB6

DDRB5

DDRB4

DDRB3

DDRB2

DDRB1

DDRB0

Write:

Reset:

000

Figure 12-6. Data Direction Register B (DDRB)

Table 12-2. Port B Pin Functions

DDRB

Bit

PTB

Bit

I/O Pin

Mode

Accesses to DDRB

Accesses to PTB

Read/Write

Read

Write

X(1)

1. X = don’t care

Input, Hi-Z(2)

2. Hi-Z = high impedance

DDRB7–DDRB0

PTB7–PTB0(3)

3. Writing affects data register, but does not affect the input.

Output

DDRB7–DDRB0

PTB7–PTB0

READ DDRB ($0005)

WRITE DDRB ($0005)

RESET

WRITE PTB ($0001)

READ PTB ($0001)

PTBx

DDRBx

PTBx

30 k

PTBPUEx

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