PI7C8150AND datasheet(90/111 Pages) PERICOM

90 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 90 of 111

APRIL 2006 – Revision 1.1

14.1.35

UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h

Bit

Function

Type

Description

19:16

64 bit addressing

R/O

0: 32 bit addressing

1: 64 bit addressing

Reset to 1

31:20

Upstream

Memory Limit

Address

R/W

Controls upstream memory limit address.

Reset to 000FFFFFh

14.1.36

UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER

– OFFSET 54h

Bit

Function

Type

Description

31:0

Upstream

Memory Base

Address

R/W

Defines bits [63:32] of the upstream memory base

Reset to 0

14.1.37

UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS

Bit

Function

Type

Description

31:0

Upstream

Memory Limit

Address

R/W

Defines bits [63:32] of the upstream memory limit

Reset to 0

14.1.38

P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h

Bit

Function

Type

Description

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

Posted Write

Parity Error

R/W

Controls PI7C8150A’s ability to assert P_SERR_L when it is unable

to transfer any read data from the target after 2

24 attempts.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set.

1: P_SERR_L is not assert if this event occurs.

Reset to 0

Posted Write

Non-Delivery

R/W

Controls PI7C8150A’s ability to assert P_SERR_L when it is unable

to transfer delayed write data after 2

24 attempts.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

06-0057

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