PI7C8150AND datasheet(48/111 Pages) PERICOM

48 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 48 of 111

APRIL 2006 – Revision 1.1

PI7C8150A does not merge bytes on separate masked write transactions to the same

DWORD address—this optimization is also best implemented in the originating

master.

PI7C8150A does not collapse sequential write transactions to the same address into a

single write transaction—the PCI Local Bus Specification does not permit this

combining of transactions.

5.2

GENERAL ORDERING GUIDELINES

Independent transactions on primary and secondary buses have a relationship only when

those transactions cross PI7C8150A.

The following general ordering guidelines govern transactions crossing PI7C8150A:

The ordering relationship of a transaction with respect to other transactions is

determined when the transaction completes, that is, when a transaction ends with a

termination other than target retry.

Requests terminated with target retry can be accepted and completed in any order with

respect to other transactions that have been terminated with target retry. If the order of

completion of delayed requests is important, the initiator should not start a second

delayed transaction until the first one has been completed. If more than one delayed

transaction is initiated, the initiator should repeat all delayed transaction requests,

using some fairness algorithm. Repeating a delayed transaction cannot be contingent

on completion of another delayed transaction. Otherwise, a deadlock can occur.

Write transactions flowing in one direction have no ordering requirements with respect

to write transactions flowing in the other direction. PI7C8150A can accept posted

write transactions on both interfaces at the same time, as well as initiate posted write

transactions on both interfaces at the same time.

The acceptance of a posted memory write transaction as a target can never be

contingent on the completion of a non-locked, non-posted transaction as a master. This

is true for PI7C8150A and must also be true for other bus agents. Otherwise, a

deadlock can occur.

PI7C8150A accepts posted write transactions, regardless of the state of completion of

any delayed transactions being forwarded across PI7C8150A.

5.3

ORDERING RULES

06-0057

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