PI7C8150AND datasheet(5/111 Pages) PERICOM

5 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 5 of 111

APRIL 2006 – Revision 1.1

TABLE OF CONTENTS

INTRODUCTION................................................................................................. 11

SIGNAL DEFINITIONS...................................................................................... 12

2.1

SIGNAL TYPES ............................................................................................................................... 12

2.2

SIGNALS ........................................................................................................................................ 12

2.2.1

PRIMARY BUS INTERFACE SIGNALS .......................................................................... 12

2.2.3

CLOCK SIGNALS ............................................................................................................... 15

2.2.4

MISCELLANEOUS SIGNALS........................................................................................... 16

2.2.5

GENERAL PURPOSE I/O INTERFACE SIGNALS ........................................................ 17

2.2.6

JTAG BOUNDARY SCAN SIGNALS ................................................................................ 17

2.2.7

POWER AND GROUND..................................................................................................... 17

2.3

PIN LIST – 208-PIN FQFP .......................................................................................................... 18

2.4

PIN LIST – 256-BALL PBGA ..................................................................................................... 20

PCI BUS OPERATION........................................................................................ 21

3.1

TYPES OF TRANSACTIONS..................................................................................................... 22

3.2

SINGLE ADDRESS PHASE ....................................................................................................... 22

3.3

DEVICE SELECT (DEVSEL_L) GENERATION ...................................................................... 23

3.4

DATA PHASE ............................................................................................................................. 23

3.5

WRITE TRANSACTIONS .......................................................................................................... 23

3.5.1

MEMORY WRITE TRANSACTIONS................................................................................ 23

3.5.2

MEMORY WRITE AND INVALIDATE ............................................................................ 24

3.5.3

DELAYED WRITE TRANSACTIONS............................................................................... 25

3.5.4

WRITE TRANSACTION ADDRESS BOUNDARIES....................................................... 26

3.5.5

BUFFERING MULTIPLE WRITE TRANSACTIONS..................................................... 26

3.5.6

FAST BACK-TO-BACK TRANSACTIONS ....................................................................... 26

3.6

READ TRANSACTIONS ............................................................................................................ 27

3.6.1

PREFETCHABLE READ TRANSACTIONS.................................................................... 27

3.6.2

NON-PREFETCHABLE READ TRANSACTIONS.......................................................... 27

3.6.3

READ PREFETCH ADDRESS BOUNDARIES ............................................................... 28

3.6.4

DELAYED READ REQUESTS .......................................................................................... 28

3.6.5

DELAYED READ COMPLETION WITH TARGET ........................................................ 29

3.6.6

DELAYED READ COMPLETION ON INITIATOR BUS................................................ 29

3.6.7

FAST BACK-TO-BACK READ TRANSACTION ............................................................. 30

3.7

CONFIGURATION TRANSACTIONS ...................................................................................... 30

3.7.1

TYPE 0 ACCESS TO PI7C8150A....................................................................................... 31

3.7.2

TYPE 1 TO TYPE 0 CONVERSION .................................................................................. 31

3.7.3

TYPE 1 TO TYPE 1 FORWARDING................................................................................. 33

3.7.4

SPECIAL CYCLES ............................................................................................................. 34

3.8

TRANSACTION TERMINATION ............................................................................................. 34

3.8.1

MASTER TERMINATION INITIATED BY PI7C8150A ................................................. 35

3.8.2

MASTER ABORT RECEIVED BY PI7C8150A ................................................................ 36

3.8.3

TARGET TERMINATION RECEIVED BY PI7C8150A.................................................. 36

3.8.3.1

DELAYED WRITE TARGET TERMINATION RESPONSE........................................ 37

3.8.3.2

POSTED WRITE TARGET TERMINATION RESPONSE ........................................... 37

3.8.3.3

DELAYED READ TARGET TERMINATION RESPONSE ......................................... 38

3.8.4

TARGET TERMINATION INITIATED BY PI7C8150A.................................................. 39

3.8.4.1

TARGET RETRY ............................................................................................................ 39

06-0057

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