PI7C8150AND datasheet(62/111 Pages) PERICOM

62 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 62 of 111

APRIL 2006 – Revision 1.1

P_SERR_L

Transaction Type

Direction

Bus Where Error

Was Detected

Primary /

Secondary Parity

Error Response

Bits

Read

Upstream

Secondary

x / x

Posted Write

Downstream

Primary

x / x

2 (asserted)

Posted Write

Downstream

Secondary

1 / 1

Posted Write

Upstream

Primary

1 / 1

Posted Write

Upstream

Secondary

x / x

Delayed Write

Downstream

Primary

x / x

Delayed Write

Downstream

Secondary

x / x

Delayed Write

Upstream

Primary

x / x

Delayed Write

Upstream

Secondary

x / x

X = don’t care

The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.

6.4

SYSTEM ERROR (SERR_L) REPORTING

PI7C8150A uses the P_SERR_L signal to report conditionally a number of system error

conditions in addition to the special case parity error conditions described in Section 6.2.3.

Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the

following conditions apply:

For PI7C8150A to assert P_SERR_L for any reason, the SERR_L enable bit must be

set in the command register.

Whenever PI7C8150A asserts P_SERR_L, PI7C8150A must also set the signaled

system error bit in the status register.

In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150A asserts

P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the

SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150A

also sets the received system error bit in the secondary status register.

PI7C8150A also conditionally asserts P_SERR_L for any of the following reasons:

Target abort detected during posted write transaction

Master abort detected during posted write transaction

Posted write data discarded after 2

24 (default) attempts to deliver (224 target retries

received)

Parity error reported on target bus during posted write transaction (see previous

section)

Delayed write data discarded after 2

24 (default) attempts to deliver (224 target retries

received)

Delayed read data cannot be transferred from target after 2

24 (default) attempts (224

target retries received)

06-0057

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