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TSI721 bảng dữ liệu(PDF) 20 Page - Renesas Technology Corp

tên linh kiện TSI721
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TSI721 bảng dữ liệu(HTML) 20 Page - Renesas Technology Corp

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Tsi721 Datasheet
20
April 4, 2016
Integrated Device Technology
2.5
S-RIO Signals
2.6
General Signals
Table 3: S-RIO Signals
Name
Pin Type
Descriptiona
a. For information on S-RIO signals that are used for power-up purposes only, see Power-up Signals.
SRTP[3:0]
SRTN[3:0]
SRIO_O
Differential transmit data for the S-RIO port.
SRRP[3:0]
SRRN[3:0]
SRIO_I
Differential receive data for the S-RIO port.
SRRSTOn
IO
It is an output for normal operation and an input during scan test mode.
As an asynchronous active-low reset output, this pin is low when four
consecutive S-RIO reset symbols are received, and SELF_RST is set to 1 in the
RapidIO PLM Port Implementation Specific Control Register
MECS
IO-PD
Asynchronous S-RIO Multicast Event Control Symbol (MECS). Its direction is
controlled by the MECS_O bit in the Device Control Register.
As an input, a rising or falling edge triggers an S-RIO MECS to be sent on the
S-RIO link. Use the RIO_PLM_SP0_MECS_FWD.SUBSCRIPTION/MULT_CS
and RIO_EM_MECS_TRIG_EN.CMD_EN to select the CMD field that should be
set with the MECS. Multiple MECSs with different CMD fields can be generated
by setting these fields appropriately.
As an output, this signal is toggled when an S-RIO MECS is received. Only a
single MECS CMD value should be selected to toggle the MECS input. Set the
RIO_EM_MECS_CAP_EN.CMD_EN to select the CMD value to be propagated
to the MECS pin. Note: Only 1 bit should be enabled in CMD_EN.
Table 4: General Signals
Name
Pin Type
Description
RSTn
I-PU
Fundamental reset (device reset).Assertion of this signal resets all logic inside
the Tsi721.
REFCLKP
REFCLKN
DIFF_I
S-RIO reference clock input. REFCLK requires a clock frequency as selected by
CLKSEL[1:0].



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