TSI721 datasheet(9/67 Pages) RENESAS

9 / 67 page

Tsi721 Datasheet

April 4, 2016

Integrated Device Technology

• Single virtual channel, VC0

• Single traffic class, TC0

— Generates only PCIe posted/non-posted TLPs with TC0

— Generates only PCIe Cpl/CplD TLPs with TC matching their requests

— Accepts PCIe TLPs with any TC

•Four BARs

— Prefetchable BAR with 32- or 64-bit addressing for PCIe-to-S-RIO bridging

— Non-prefetchable BAR with 32- or 64-bit addressing for PCIe-to-S-RIO bridging

— Non-prefetchable BAR with 32-bit addressing for PCIe MWr to S-RIO doorbell bridging

— Non-prefetchable BAR with 32-bit addressing for Tsi721 internal register access

• Initial credit advertisement programmable through EEPROM

• Dynamic control of credits through registers

• Starvation prevention based on flow control credit updates

• Large buffers

— 12 KB/2 KB/12 KB input buffers for up to 127 posted/non-posted/completion TLPs

— 12 KB/2 KB/12 KB output buffers for up to 128 posted/non-posted/completion TLPs

• Debug features

— Slave analog loopback through a control register

— Slave loopback using TS1/TS2 ordered sets

— Master loopback

— Internal error reporting

— ECC protection on internal memories

1.2.2

S-RIO Features

• S-RIO 2.1 standard compliant

• 5/3.125/2.5/1.25 Gbaud link speed

• x4/x2/x1 link width

• 34-, 50-, and 66-bit addressing

• 16 destID filters

• 8 S-RIO flows

• 9-KB ingress buffer (32 x 288)

• 9-KB egress buffer (32 x 288)

• Lane reversal

• Lane polarity inversion

1.2.3

Bridging Features

• Store and forward from PCIe to S-RIO

• Store and forward from S-RIO to PCIe

• Line rate support for 64 byte and larger packets

• 32 outstanding PCIe requests to root complex

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