TSI721 datasheet(31/67 Pages) RENESAS

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Tsi721 Datasheet

April 4, 2016

Integrated Device Technology

3.6

Decoupling Recommendation

Table 17 provides the recommended decoupling for the Tsi721. Use low ESR, low lead inductance ceramic capacitors with

X7R or X5R rating.

3.7

AC Timing Specifications

This section describes the AC timing specifications and electrical characteristics for the Tsi721.

3.7.1

PCIe Differential Receiver Specifications

Table 18 lists the electrical characteristics for the PCIe differential receivers in the Tsi721. Parameters are defined separately

for 2.5 Gbps and 5.0 Gbps implementations. Table 18 is duplicated from the PCI Express Base Specification (Rev. 2.1) Section

4.3.3.4 Table 4-12 on page 270.

Table 17: Decoupling Recommendation

Rail

Decoupling

VDDIO

5x 0.1uF and 1x 10uF

AVTT

5x 0.1uF and 1x 10uF

VDD

5x 0.1uF and 1x 10uF

AVDD10

5x 0.1uF and 1x 10uF

AVDD25

5x 0.1uF and 1x10uF

Table 18: PCIe Differential Receiver Specifications

Symbol

Parameter

2.5 Gbps

5.0 Gbps

Unit

Notes

Min.

Max.

Min.

Max.

Unit interval

399.88

400.12

199.94

200.06

UI does not account for SSC caused

variations

VRX-DIFF-PP-CC Differential Rx peak-peak

voltage

0.175

1.2

0.120

1.2

See section 4.3.7.2.2 of the PCI

Express Base Specification (Rev. 2.1)

VRX-DIFF-PP-DC Differential Rx peak-peak

voltage for data clocked

Rx architecture

0.175

1.2

0.100

1.2

See section 4.3.7.2.2 of the PCI

Express Base Specification (Rev. 2.1)

TRX-EYE

Receiver eye time

opening

0.40

N/A

Minimum eye time at Rx pins to produce

a 10-12 BER. See Note 1.

TRX-TJ-CC

Maximum Rx inherent

timing error

N/A

0.40

Maximum Rx inherent total timing error

for common Refclk Rx architecture. See

Note 2.

TRX-TJ-DC

Maximum Rx inherent

timing error

N/A

0.34

Maximum Rx inherent total timing error

for data clocked Rx architecture. See

Note 2.

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