PCF5271CVM100 datasheet(18/56 Pages) FREESCALE

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MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Modes of Operation

Freescale Semiconductor

5.2

Low Power Modes

The following features are available to support applications which require low power.

•

Four modes of operation:

—RUN

—WAIT

— DOZE

—STOP

•

Ability to shut down most peripherals independently.

•

Ability to shut down the external CLKOUT pin.

There are four modes of operation: RUN, WAIT, DOZE, and STOP. The system enters a low power mode

when the user programs the low power bits (LPMD) in the LPCR (Low Power Control Register) in the

CIM before the CPU core executes a STOP instruction. This idles the CPU with no cycles active. The

LPMD bits indicate to the system and clock controller to power down and stop the clocks appropriately.

During STOP mode, the system clock is stopped low.

A wakeup event is required to exit a low power mode and return back to RUN mode. Wakeup events

consist of any of the following conditions. See the following sections for more details.

1. Any type of reset.

2. Assertion of the BKPT pin to request entry into Debug mode.

3. Debug request bit in the BDM control register to request entry into debug mode.

4. Any valid interrupt request.

5.2.1

RUN Mode

RUN mode is the normal system operating mode. Current consumption in this mode is related directly to

the frequency chosen for the system clock.

D25, D24

Select chip select /

address line

00 PADDR[7:5] configured

as A23-A21 (default)

10 PADDR7 configured as

CS6,

PADDR[6:5] as A22-A21

01 PADDR[7:6] configured

as CS[6:5],

PADDR5 as A21

11 PADDR[7:5] configured

as CS[6:4]

JTAG_EN

Selects BDM or

JTAG mode

0BDM mode

1 JTAG mode

Table 3. Configuration Pin Descriptions (continued)

Chip Configuration

Function

Pin State/Meaning

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