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PCF5271CVM100 bảng dữ liệu(PDF) 12 Page - Freescale Semiconductor, Inc |
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PCF5271CVM100 bảng dữ liệu(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 56 page ![]() MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Signal Descriptions Freescale Semiconductor 12 3.20 GPIO Unused bus interface and peripheral pins on the MCF5271 can be used as discrete general-purpose inputs and outputs. These are managed by a dedicated GPIO module that logically groups all pins into ports located within a contiguous block of memory-mapped control registers. All of the pins associated with the external bus interface may be used for several different functions. Their primary function is to provide an external memory interface to access off-chip resources. When not used for this, all of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported. The digital I/O pins on the MCF5271 are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins. 4 Signal Descriptions This section describes signals that connect off chip, including a table of signal properties. For a more detailed discussion of the MCF5271 signals, consult the MCF5235 Reference Manual (MCF5235RM). 4.1 Signal Properties Table 2 lists all of the signals grouped by function. The “Dir” column is the direction for the primary function of the pin. Refer to Section 7, “Mechanicals/Pinouts and Part Numbers,” for package diagrams. NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality. Table 2. MCF5270 and MCF5271 Signal Information and Muxing Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA Reset RESET — — — I 83 N13 RSTOUT — — — O 82 P13 Clock EXTAL — — — I 86 M14 XTAL — — — O 85 N14 |
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