PCF5271CVM100 datasheet(16/56 Pages) FREESCALE

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MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Modes of Operation

Freescale Semiconductor

Modes of Operation

5.1

Chip Configuration Mode—Device

Operating Options

•

Chip operating mode:

— Master mode

•

Boot device/size:

— External device boot

– 32-bit

– 16-bit (Default)

–8-bit

•

Output pad strength:

PST[3:0]

—

77:74

M11, N11, P11,

L10

Test

TEST

—

PLL_TEST

—

Power Supplies

VDDPLL

—

M13

VSSPLL

—

L14

OVDD

—

1, 18, 32, 41, 55,

69, 81, 94, 105,

114, 128, 138,

145

E5, E7, E10, F7,

F9, G6, G8, H7,

H8, H9, J6, J8,

J10, K5, K6, K8

VSS

—

17, 31, 40, 54,

67, 80, 88, 93,

104, 113, 127,

137, 144, 160

A1, A14, E6, E9,

F6, F8, F10, G7,

G9, H6, J5, J7,

J9, K7, P1, P14

VDD

—

16, 53, 103

D6, F11, G4, L4

NOTES:

Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled

in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO

module is not responsible for assigning these pins.

Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1 Alternate 2 Dir.1

MCF5270

MCF5271

160 QFP

MCF5270

MCF5271

196 MAPBGA

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