| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
PCF5271CVM100 bảng dữ liệu(PDF) 36 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
PCF5271CVM100 bảng dữ liệu(HTML) 36 Page - Freescale Semiconductor, Inc |
|
36 / 56 page ![]() MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Preliminary Electrical Characteristics Freescale Semiconductor 36 8.4 Oscillator and PLLMRFM Electrical Characteristics Table 29. HiP7 PLLMRFM Electrical Specifications1 NOTES: 1 All values given are initial design targets and subject to change. Num Characteristic Symbol Min. Value Max. Value Unit 1 PLL Reference Frequency Range Crystal reference External reference 1:1 mode (NOTE: fsys/2 = 2 × fref_1:1) fref_crystal fref_ext fref_1:1 8 8 24 25 25 50 MHz 2 Core frequency CLKOUT Frequency 2 External reference On-Chip PLL Frequency 2 All internal registers retain data at 0 Hz. fsys fsys/2 0 fref / 32 100 50 50 MHz MHZ MHz 3 Loss of Reference Frequency 3, 5 3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode. fLOR 100 1000 kHz 4 Self Clocked Mode Frequency 4, 5 4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings. fSCM 10.25 15.25 MHz 5 Crystal Start-up Time 5, 6 5 This parameter is guaranteed by characterization before qualification rather than 100% tested. 6 Proper PC board layout procedures must be followed to achieve specifications. tcst —10 ms 6 XTAL Load Capacitance5 530 pF 7 PLL Lock Time 5, 7,13 tlpll —750 µs 8 Power-up To Lock Time 5, 6,8 With Crystal Reference (includes 5 time) Without Crystal Reference9 tlplk — — 11 750 ms µs 9 1:1 Mode Clock Skew (between CLKOUT and EXTAL) 10 tskew –1 1 ns 10 Duty Cycle of reference 5 tdc 40 60 % 11 Frequency un-LOCK Range fUL –3.8 4.1 % fsys/2 12 Frequency LOCK Range fLCK –1.7 2.0 % fsys/2 13 CLKOUT Period Jitter, 5, 6, 8,11, 12 Measured at fsys/2 Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) Cjitter — — 5.0 .01 % fsys/2 14 Frequency Modulation Range Limit13,14 (fsys/2 Max must not be exceeded) Cmod 0.8 2.2 %fsys/2 15 ICO Frequency. fico = fref * 2 * (MFD+2) 15 fico 48 75 MHz |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |