PCF5271CVM100 datasheet(25/56 Pages) FREESCALE

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Design Recommendations

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Freescale Semiconductor

6.7.1.3

SDRAM Interfacing Example

The tables in the previous section can be used to configure the interface in the following example. To

interface one 2M 32-bit 4 bank SDRAM component (8 columns) to the MCF5271, the connections would

be as shown in Table 22.

6.7.2

Ethernet PHY Transceiver Connection

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10

Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3

standard defines and the FEC module supports 18 signals. These are shown in Table 23.

Table 19. MCF5271MCF5271 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)

MCF5271

Pins

A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

13121110

17192122

25262728

3031

Column

2345

678

SDRAM

Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

Table 20. MCF5271MCF5271 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)

MCF5271

Pins

A15 A14 A13 A12 A11 A10

A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

345

678

SDRAM

Pins

A10 A11 A12 A13 A14 A15 A16 A17 A18

Table 21. MCF5271MCF5271 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)

MCF5271

Pins

A15 A14 A13 A12 A11 A10

A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31

Row

1413

1719

212325

262728

293031

Column

1618

202224

SDRAM

Pins

A10 A11 A12 A13 A14 A15 A16 A17

Table 22. SDRAM Hardware Connections

SDRAM

Pins

A10 = CMD

BA0

BA1

MCF5271

Pins

A15

A14

A13

A12

A11

A10

A17

A18

A19

A20

A21

A22

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