PCF5271CVM100 datasheet(7/56 Pages) FREESCALE

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Features

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Freescale Semiconductor

—Reset

– Separate reset in and reset out signals

– Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of

clock, PLL loss of lock

– Status flag indication of source of last reset

•

General Purpose I/O interface

— Up to 61 bits of general purpose I/O

— Bit manipulation supported via set/clear functions

— Unused peripheral pins may be used as extra GPIO

•

JTAG support for system level board testing

3.2

V2 Core Overview

The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The

two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction

fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting

execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage

decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction

execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a

separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the

MCF5271 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing

capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations,

with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned

integers as well as signed fractional operands as well as a complete set of instructions to process these data

types. The EMAC provides superb support for execution of DSP operations within the context of a single

processor at a minimal hardware cost.

3.3

Debug Module

The ColdFire processor core debug interface is provided to support system debugging in conjunction with

low-cost debug and emulator development tools. Through a standard debug interface, users can access

real-time trace and debug information. This allows the processor and system to be debugged at full speed

without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface

provided on Freescale’s 683xx family of parts.

The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers

(with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask

the dedicated debug serial communication channel or from the processor’s supervisor mode programming

model. The breakpoint registers can be configured to generate triggers by combining the address, data, and

PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to

generate a processor halt or initiate a debug interrupt exception.

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