ISL73141SEH

5. Applications Information

R34DS0012EU0402 Rev.4.2

Page 24 of 27

Feb 23, 2023

It is important to understand the settling time associated with the analog input of the ISL73141SEH and the

impacts of RS and CP. To allow the ISL73141SEH to accurately resolve the input signal, it is important that the

input signal is settled completely before the signal is sampled by the ISL73141SEH. To meet the datasheet

specifications, the settling time must be met for the input signals on the analog input of the ISL73141SEH. To

accurately resolve to 1 LSB, the settling time is defined by Equation 3:

Simplifying this results in Equation 4:

Solving for t results in:

, which can be written as

and further simplified to

.

Settling time is t, RS ×CP is τ, and the resolution of the ADC is N.

The ISL73141SEH is a 14-bit ADC, which means the settling time to attain 1 LSB accuracy is 9.7 × τ. For

example, the ISL73141SEHEV1Z evaluation board employs a 24Ω resistor for RS and a 470pF capacitor for CP,

which means that the required settling time would be t = 0.693 × 14 × 24Ω × 470pF = 109.4ns. If different RS and

CP values are used, calculate the settling time for those conditions. These calculations assume the settling time of

the input network RS and CP are much larger than the settling time of any amplifier driving the ISL73141SEH

analog input. If this is not the case, the settling time of the input network must be root-sum-squared with the

settling time of the amplifier to determine the required settling time using Equation 5:

5.10 Package

The ISL73141SEH is available in a 14 Ld hermetically sealed Ceramic Dual Flatpack (CDFP) package (see

Package Outline Drawing). Pin 14 (GND) is connected to the package seal ring and the package lid.

Figure 57. ISL73141SEH Common-Mode Conversion Amplifier Example Circuit

AV = +2

AV = -2

+

-

-

+

AV = 1

-

+

VREF

AIN

GND

ISL73141SEH

R

R

2R

R

5R

R

0V

+VREF/4

-VREF/4

Analog

Input

VREF/2

+VREF

0V

RS

CP

(EQ. 3)

1

2

N

-------

e

t

–





=

(EQ. 4)

2

N



ln

t



--

–

=

t-



2

N



ln



=

tN





2





ln



=

t0.693 N





=

(EQ. 5)

ttAMP



2

tRC



2

+

=