ISL73141SEH

5. Applications Information

R34DS0012EU0402 Rev.4.2

Page 20 of 27

Feb 23, 2023

5.

Applications Information

5.1

Overview

The ISL73141SEH is a radiation hardened, high precision, low noise, 14-bit Successive Approximation Register

(SAR) ADC. The device operates from an analog supply voltage range of 3V to 3.6V or 4.5V to 5.5V, a digital

supply voltage range of 2.2V to 3.6V, and has a dedicated reference input (REF). The ISL73141SEH supports

sample rates up to 1Msps with an analog supply voltage range of 4.5V to 5.5V. It also supports sample rates up to

750ksps with an analog supply voltage range of 3V to 3.6V, which allows you to optimize your system based on

the range of the analog signal being sampled. The ISL73141SEH samples at a rate of 1Msps and achieves

excellent dynamic performance (82.1dB SNR, 100dB THD) and linearity (INL ±1LSB, DNL ±0.5 LSB) while still

maintaining a low power consumption of 60mW from a 5V supply. Additionally, the device offers a Sleep mode

that minimizes power consumption to <50µW during idle operation.

The IS73141SEH offers a high-speed serial interface with an independent digital supply (DVCC) range of 2.2V to

3.6V, making it ideal to interface to 2.5V or 3.3V systems. The conversion data is output on the SDO pin with no

latency. The ISL73141SEH supports up to a 50MHz serial data read clock on the SCK input.

The single-ended analog input voltage (AIN) is sampled on the falling edge of CS. The input range of the

ISL73141SEH is determined by the REF pin voltage to GND. The ISL73141SEH supports excellent THD and

SFDR sampling input signal frequencies up to and beyond Nyquist (such as fIN ≥ 500kHz with fSAMP = 1Msps).

The ISL73141SEH uses the external reference input (REF) as the positive reference and the GND pin of the

device as the negative reference.

5.2

Serial Interface and BUSY

The ISL73141SEH uses a 3-wire serial port interface to communicate with other devices such as microcontrollers

and other external circuitry. A falling edge on CS initiates conversion in the ISL73141SEH. Renesas requires

holding CS high for at least 40ns before initiating the conversion. The conversion is timed by an internal oscillator.

During the conversion process, the BUSY signal is asserted high. When the conversion is complete, BUSY is

de-asserted. Renesas requires holding SCK low during tCONV. When BUSY is de-asserted, the MSB is

immediately available on the SDO pin. Each subsequent rising edge of SCK serially outputs data on SDO from

the MSB-1 to the LSB. The input logic level of CS and SCK is determined by the DVCC supply voltage that

operates across a range of 2.2V up to 3.6V. Similarly, the output voltage level of BUSY is also determined by the

DVCC supply voltage.

5.3

Operational Phases and Timing

The conversion result MSB is available for serial readout at the SDO pin immediately following a completed

conversion. The BUSY indicator flag is high during conversion, and transitions low following completion of the

conversion. When the BUSY indicator flag goes LOW after a conversion, the MSB of the conversion result (B13)

is immediately available at the SDO pin. Subsequent rising edges of SCK shift bits MSB-1 (B12) through the LSB

(B0) to SDO for readout. The output voltage level of SDO is determined by the DVCC supply voltage which

operates across a range of 2.2V up to 3.6V. Figure 54 shows the basic timing of the ISL73141SEH in a

conversion cycle.