ISL73141SEH

5. Applications Information

R34DS0012EU0402 Rev.4.2

Page 21 of 27

Feb 23, 2023

The following are the three phases of operation in the ISL73141SEH that are shown in Figure 54.

• Acquisition

•Conversion

• Readout

The Acquisition phase begins immediately following the completion of the conversion. During CS high, the SDO

pin is held in high impedance (high-Z). The falling edge of CS defines the sampling instant of the ISL73141SEH,

initiates a conversion, and also enables the SDO output to a low state. The conversion cycle is internally timed

through an internal oscillator and takes an ensured maximum time of tCONV to complete. Following conversion,

several internal blocks are powered down to reduce power consumption. This phase of power-down is referred to

as NAP mode. The ISL73141SEH stays in NAP mode until the next rising edge of CS where the ISL73141SEH is

fully powered up.

The following is an example of timing calculation in an application operating the ISL73141SEHMF7 at 1Msps.

When deriving timing it is imperative to use the appropriate maximum and minimum specifications. The CS input

must be held high for 40ns (tCSH). The time between the falling edge of CS and the rising edge of BUSY is a

maximum of 30ns (tBUSYLH). The conversion time (tCONV) is a maximum of 660ns. To clock the data out of the

ADC there must be 14 rising edges of SCK (tREADOUT). The 14th SCK falling edge must be coincident with the

rising edge of CS for the subsequent sample. Using the maximum SCK frequency of 50MHz yields:

Note: The 14th SCK edge is coincident with the rising edge of CS so there is only a 1/2 period for the 14th SCK.

To calculate and validate the sample timing use Equation 1:

For a sample rate of 1Msps using the timing calculates to:

Figure 54. ISL73141SEH Timing Diagram

12

13

14

12

SCKL

t

SCKH

t

t

SCK

HI-Z

HI-Z

CS

SCK

SDO

CSH

t

t

CONV

READOUT

t

tCYC

B13

B12

B0

B1

B2

B3

t DBUSYLSDOV

tHSDOV

t

DCSLSDOL

tDCSHSDOZ

Serial Data Bits B[13:0] Correspond to the Current Conversion

t

BUSYLH

BUSY

t QUIET

Acquire

Convert

Nap and Readout

Acquire

CSH

t

t

DSCKSDOV

13 20ns 10ns

+



270ns

=

(EQ. 1)

tCYC

tCSH tBUSYLH tCONV tREADOUT

++

+

=

tCYC

40ns 30ns 660ns 270ns

1000ns

=

++

+

=