ISL73141SEH

2. Pin In formation

R34DS0012EU0402 Rev.4.2

Page 5 of 27

Feb 23, 2023

3

REF

1

Reference input. The input range of REF is 1.95V to AVCC for the ISL73141SEHMFN and 3.9V

to 4.2V for the ISL73141SEHMF7. The voltage at the REF pin (VREF) defines the input range of

the analog input as 0V to VREF. Bypass REF to GND with a low ESR 10µF ceramic capacitor.

5

AIN

1

Analog input. AIN supports an input voltage range of 0V to VREF.

8CS

2

Convert Start Low input. A falling edge on this input starts a new conversion. The conversion is

timed using an internal oscillator. The device automatically powers down following the

conversion process. The logic state of the CS pin controls the state of the SDO pin. A logic high

on the CS pin disables the SDO pin driver and the SDO pin impedance is Hi-Z. A logic low on

the CS pin enables the SDO driver (unless PD is low) and allows data to be read out following a

conversion.

7PD

2

Power-down low input. When this pin is brought low the ADC enters power-down mode. If this

occurs during a conversion, the conversion is halted and the SDO pin is placed in Hi-Z. Logic

levels are determined by DVCC.

9

BUSY

3

Busy output. A logic high indicates a conversion is in progress. The BUSY indicator returns low

following the completion of a conversion. Logic levels are determined by DVCC.

11

SCK

2

Serial data clock input. When CS is low and the BUSY indicator is low, the conversion result is

shifted out on SDO on the rising edges of SCK, Most Significant Bit (MSB) first to Least

Significant Bit (LSB) last. Logic levels are determined by DVCC. SCK should be held low when it

is not being asserted.

12

SDO

3

Serial data output. The current conversion result is serially shifted out on this pin on the rising

edges of SCK, MSB first to LSB last. The data stream is composed of 14 bits of conversion data

followed by trailing zeros. Logic Levels are determined by DVCC.

13

DVCC

1

Digital I/O supply. Voltage range on this pin is 2.2V to 3.6V. DVCC is nominally set to the same

supply voltage as the host interface (2.5V or 3.3V). Bypass DVCC to GND with 0.1µF capacitor.

LID

N/A

N/A

Package Lid is internally connected to GND through Pin 14.

Pin Number

Pin Name

ESD

Circuit

Description

Circuit 1

Pins

1, 3, 5, 13

Circuit 2

Circuit 3

Pins

7, 8, 11

600Ω

DVCC

Pins

9, 12