ISL73141SEH

3. Specifications

R34DS0012EU0402 Rev.4.2

Page 11 of 27

Feb 23, 2023

3.5.2

3.3V Operation

3.6

Timing Diagrams

AVCC = 3.0V to 3.6V; DVCC = 2.2V to 3.6V, REF = 3.0V, GND = 0V, fSAMP = 750ksps, AIN = -1dBFS; TA = -55°C to +125°C, unless otherwise

noted.

Parameter

Symbol

Test Conditions

Min

(Notes 9, 10)

Typ

(Note 8)

Max

(Notes 9, 10)Unit

Timing Characteristics

Maximum Sampling Frequency

fSAMP

750

kHz

Conversion Time

tCONV

BUSY Output High Time

760

850

ns

CS High Time

tCSH

50

ns

SCK Held Low to CS↓

tQUIET

50

ns

CS Falling Edge to BUSY↑

tBUSYLH

CL = 10pF

21

40

ns

SCK Period

tSCK

30

ns

SCK High Time

tSCKH

12

ns

SCK Low Time

tSCKL

12

ns

SDO Data Valid Delay from BUSY↓

tDBUSYLSDOV CL = 10pF

-5

0

ns

SDO Data Valid Delay from SCK↑

tDSCKSDOV CL = 10pF

25

ns

SDO Data Valid Hold Time from

SCK↑

tHSDOV

CL = 10pF

8

16

ns

SDO Bus Acquisition Time from CS↓

tDCSLSDOL

CL = 10pF

12

30

ns

SDO Bus Relinquish Time after CS↑

tDCSHSDOZ CL = 10pF

14

30

ns

Wake-Up time from Power-Down

Mode

tWAKE

Time to wait after PD↑ to first

sample

20

µs

Figure 5. ISL73141SEH Operational Timing Diagram

12

13

14

12

SCKL

t

SCKH

t

t

SCK

HI-Z

HI-Z

CS

SCK

SDO

CSH

t

t

CONV

READOUT

t

tCYC

B13

B12

B0

B1

B2

B3

t DBUSYLSDOV

tHSDOV

t

DCSLSDOL

tDCSHSDOZ

Serial Data Bits B[13:0] Correspond to the Current Conversion

t

BUSYLH

BUSY

t QUIET

Acquire

Convert

Nap and Readout

Acquire

CSH

t

t

DSCKSDOV