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ZAMC4100GA2R bảng dữ liệu(PDF) 126 Page - Renesas Technology Corp |
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ZAMC4100GA2R bảng dữ liệu(HTML) 126 Page - Renesas Technology Corp |
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126 / 156 page ![]() ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 126 January 26, 2016 Table 4.11 Register [0x4000_1408] GPIO_OUT GPIO_OUT ADD:0x4000_1408 Bit Name Ext. Access Int. Access Reset Value Description 7 : 0 GPIOOUT R / W R 0 Value to be driven out of each GPIO. 15 : 8 --- N/A N/A 0 Reserved. 31 : 16 --- R --- 0 Unused; always read as 0. Table 4.12 Register [0x4000_140C] GPIO_SETCLR GPIO_SETCLR ADD:0x4000_140C Bit Name Ext. Access Int. Access Reset Value Description 7 : 0 SETOUT R / W R 0 Writing a 1 to the corresponding bit will set the GPIO output to 1. Lower priority than clear. Always read as 0. 15 : 8 --- N/A N/A 0 Reserved. 23 : 16 CLROUT R / W R 0 Writing a 1 to the corresponding bit will set the GPIO output to 0. Higher priority than set. Always read as 0. 31 : 24 --- N/A N/A 0 Reserved. Table 4.13 Register [0x4000_1410] GPIO_IRQSTAT GPIO_IRQSTAT ADD:0x4000_1410 Bit Name Ext. Access Int. Access Reset Value Description 7 : 0 IRQSAT RC R/W 0 This register reflects the interrupt status of each GPIO that is enabled as interrupt. Reading this register will clear the interrupt status bit. 15 : 8 --- N/A N/A 0 Reserved. 31 : 16 --- R --- 0 Unused; always read as 0. |
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