ZAMC4100GA2R datasheet(41/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

Table 3.4

WDTCONF Register Bits Description

Bit

Description

WDTCLR: WDT clear bit. Toggling this bit periodically to clear the WDT in order to avoid MCU reset.

1 = Next written value should be 0.

0 = Next written value should be 1.

Note: The WDTLCK bit does not lock the write for the WDTCLR bit.

6:5

SWDPOS: WDT post-scaler for system time-out reset generation.

00 = No system reset generated by the WDT.

01 = System reset is generated at each MCU reset by the WDT.

10 = System reset is generated after 4 consecutive MCU resets.

11 = System reset is generated after 8 consecutive MCU resets.

4:2

MWDPOS: WDT postscaler for MCU time-out reset generation.

000 = 1:1

WDT time-out after 10 ms.

001 = 1:2

WDT time-out after 20 ms.

010 = 1:4

WDT time-out after 40 ms.

011 = 1:8

WDT time-out after 80 ms.

100 = 1:16

WDT time-out after 160 ms.

101 = 1:32

WDT time-out after 320 ms.

110 = 1:64

WDT time-out after 640 ms.

111 = 1:128 WDT time-out after 1280 ms.

Note: WDT time-out period is calculated for the typical value of the OSCL frequency.

WDTLCK: WDT configuration lock bit.

1 = The writing to the WDTCONF register is not possible and writing can be enabled only after a power-on reset.

0 = The write access of WDTCONF is enabled.

WDTEN: WDT enable bit.

1 = The WDT is enabled, and if a time-out occurs, it will generate an MCU reset.

0 = The WDT is disabled. No reset is generated by WDT.

3.4.

System Supply Monitoring

The ZAMC4100 continuously monitors the supply at the VDDE pin. If the VDDE voltage crosses the upper or

lower ends of the supply range (see Table 1.5), an over-voltage or under-voltage interrupt is generated. In

addition, the charge pump voltage is monitored for being in or out of range.

3.4.1.

Over-Voltage and Under-Voltage Detection

If an over-voltage or under-voltage event occurs, it is indicated in the OVIF and UVIF flags respectively in the

RSTSTAT register (see Table 3.1). Both interrupt flags in an OR-function generate the supply error interrupt flag

(SEIF), which is accessible via the IRQSTAT register (see

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