ZAMC4100GA2R datasheet(114/156 Pages) RENESAS

114 / 156 page

ZAMC4100 Datasheet

114

January 26, 2016

4.8.

Master SPI Module

4.8.1.

Overview

The integrated SPI is a pure four-wire master interface that is used for communication with the SBC. As shown in

Figure 4.5, the three lines SPICLK, MOSI, and MISO are fully controlled by hardware while the chip select CSN

line is controlled by software in accordance with the setup time requirement as per SPI bus timing (for

specifications, see section 1.3.3).

Figure 4.5 Master SPI Block Diagram

SPICFG

SPISTAT

SPICLKCFG

SHIFTREG

SPIDATA

RxBUF

TxBUF

SPI

CONTROL

LOGIC

SPICLK

CSN

MOSI

MISO

SBC

SPI SLAVE

MCU

SBC

IRQ

4.8.2.

Setup Requirements for the Slave SPI of SBC

For compatibility with the SBC SPI SLAVE, the following settings must be made in the MCU SPI MASTER:

•

Clock phase = 1 and clock polarity = 1. This is the default configuration (after MCU reset) implemented

via the CPHA and CPOL bits of the Z1_SPICLKCFG register respectively (Table 4.23).

•

SPI clock frequency calculated by the formula:

(

)

∗

CDIV

OSCH

SPICLK

Where CDIV is the clock divider value bit field in the Z1_SPICLKCFG register.

Note: For the SPI to operate within its valid speed range, the value programmed in CDIV must not be less than 2.

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