ZAMC4100GA2R datasheet(110/156 Pages) RENESAS

tên linh kiện	ZAMC4100GA2R

Giải thích chi tiết về linh kiện	Actuator and Motor Controller

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ZAMC4100 Datasheet

110

January 26, 2016

4.4.

MCU INTERRUPTS

4.4.1.

Interrupts Organization

Figure 4.4 shows the peripheral interrupts with the related control and status registers. Each peripheral has a

unique IRQ line that is attached to dedicated interrupt lines 0 to 5, which go to the nested vector interrupt

controller (NVIC) module within the ARM® CORTEX™-M0 processor. For more information about the NVIC, refer

to the NVIC chapter of the ARM® CORTEX™-M0 Document Kit.

Figure 4.4 MCU Interrupt Logic Organization

Line 0

Line 1

Line 2

Line 3

Line 4

Line 5

FLASH

SW-LIN

SPI

32 BIT TIMER

GPIO

IRQEN

IRQEDGE

Z1_LINIRQEN

Z1_LINSTAT

Z1_SPISTAT

Z1_SPICFG

Peripherals

ARM® CORTEX™-M0 CORE

SBC

Interrupt

Controller

SBC

NVIC

Interrupt

Controller

CORTEX™-M0

PROCESSOR

TIMER MODULE

(Counter Overflow)

FC-IRQ-EN

FC-STAT-CORE

NMI

ECC

PROG: Double Bit Error

MCU

CONTAINS IRQ EN BITS

IRQN

Note: The Systick has an NVIC number of -1 which is within the Cortex™-M0 core. For more details, refer to the

ARM® CORTEX™-M0 Document Kit.

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