HIP2210, HIP2211

6. PCB Layout Guidelines

FN9347 Rev.1.01

Page 22 of 27

Jun.23.20

6.

PCB Layout Guidelines

The AC performance of the HIP2210/HIP2211 depends significantly on the design of the PCB. The following

layout design guidelines are recommended to achieve optimum switching performance:

• It may be necessary to add resistance to dampen resonating parasitic circuits. PCB designs with long trace

lengths on the LO and HO outputs may require series gate resistors on the bridge FETs to dampen the

oscillations. It is good practice to place 0Ω chip resistors in series with the HO and LO driver outputs to the

MOSFET gates.

• The routing of the half-bridge switching phase node to the HIP2210/HIP2211 HS pin should implement optimum

layout practices. The PCB trace should be short and wide to minimize lead inductance. Also, route the HO trace

directly above or below the HS trace to minimize ground loops.

• Understand how power currents flow. The high amplitude di/dt currents of the half-bridge FETs induce

significant voltage transients on the associated traces and ground planes. Keep these high current paths away

from sensitive low voltage signal traces.

• Avoid paralleling high di/dt traces with low-level signal lines. High di/dt induces currents in the low-level signal

lines.

• Keep power loops as short as possible by routing the source and return traces on adjacent layers, directly

above and beneath each other.

• When practical, minimize impedances in low-level signal circuits. The noise magnetically induced on a 10k

resistor is 10x larger than the noise on a 1k resistor.

• Be aware of magnetic fields emanating from transformers and inductors. Core gaps in these structures are

especially bad for emitting flux.

• If you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines.

• Use low inductance components such as SMD chip resistors and chip capacitors with low Equivalent Series

Inductance (ESL).

• Use decoupling capacitors to reduce the influence of parasitic inductance. To be effective, these capacitors

must also have the shortest possible lead lengths to the component pins. If vias are used, connect several

paralleled vias to reduce their inductance.

• Keep high dv/dt nodes away from low-level circuits. Guard ringing and/or shielding can be used to shunt away

dv/dt injected currents from sensitive circuits. This is especially true for the RDT pin and resistor, and also the

PWM and HI/LI signals.

• Avoid having a signal ground plane under a high dv/dt circuit. This injects high di/dt currents into the signal

ground paths.

• Calculate power dissipation and voltage drop calculations for the power traces. Most PCB/CAD programs have

built-in tools for calculation of trace resistance.

• Large power components (power FETs, electrolytic capacitors, power resistors, etc.) have internal parasitic

inductance, which cannot be eliminated. Accounted for this in the PCB layout and circuit design.

• If you simulate your circuits, consider including parasitic components.

• If available, connect the EPAD on the bottom side of the package to the PCB ground plane with thermal vias for

heat removal.