HIP2210, HIP2211

4. Functional Description

FN9347 Rev.1.01

Page 17 of 27

Jun.23.20

4.

Functional Description

4.1

Gate Drive for NMOS Half-Bridge

The HIP2210 and HIP2211 are NMOS FET drivers for half-bridge, full-bridge, two-switch forward, active clamp, or

synchronous buck configurations. In half-bridge configurations, the gate of the low-side FET requires a ground

referenced signal above the gate threshold voltage to switch on and off. The high-side FET source terminal is

connected to the drain of the low-side FET and is called the Phase or Switch node. When the high-side FET is on,

its source terminal is at the high voltage supply. The gate drive of the high-side FET requires a floating bootstrap

supply to properly drive the high-side FET gate voltage relative to its source terminal. A bootstrap circuit is

implemented on these drivers to properly switch the high-side and low-side NMOS FETs.

4.2

Functional Overview

The HIP2210 and HIP2211 drivers are designed to switch NMOS FETs in up to 100V half-bridge configurations.

The drivers feature strong 3A sourcing and 4A sinking output drive capability and fast 15ns propagation delay

times to switch low rDS(ON) NFETs for up to 1MHz applications. With an integrated bootstrap diode, the floating

high-side bias requires only an external bootstrap capacitor to properly drive the high-side FET.

The drivers have integrated UVLO on both the VDD and Boot supply to prevent low gate voltage drive to the

NFETs. The HIP2210 and HIP2211 can operate across a wide VDD voltage range of 6V to 18V.

The HIP2211 has 3.3V CMOS compatible HI and LI inputs to control the high-side and low-side driver outputs,

respectively.

The HIP2210 features a single tri-level PWM input to control the high-side and low-side drivers. The tri-level

thresholds are set by an external VREF pin, which allows PWM control from 2.7V to 5.5V logic supply voltages.

When PWM is high, the high-side driver is sourcing and the low-side driver is sinking. When PWM is low, the

low-side driver is sourcing and the high-side driver is sinking. When PWM is at mid-level, both driver outputs are

sinking to put the half-bridge in a high impedance state. The HIP2210 also has an EN pin to enable the input logic

control, or disable it and place the half-bridge in high impedance state. This EN pin feature is useful to prevent

false switching of the NFETs during controller start-up. See “Applications Information” on page 18 for more

information about the PWM input control.

The HIP2210 controls dead time with an adjustable dead time delay pin (RDT). A resistor to ground sets a dead

time delay of the rising edge of the driver output. See Applications Information for more information about setting

the adjustable dead time delay.