HIP2210EVAL1Z datasheet(5/28 Pages) RENESAS

5 / 28 page

HIP2210, HIP2211

1. Overview

FN9347 Rev.1.01

Page 5 of 27

Jun.23.20

1.4

Pin Descriptions

HIP2211FR8Z

(8 Ld 4x4 DFN)

Top View

HIP2210FRTZ

(10 Ld 4x4 TDFN)

Top View

Name

Pin Number

Description

HIP2210

HIP2211

10 Ld DFN 10 Ld DFN 8 Ld SOIC 8 Ld DFN

VDD

Analog input supply voltage and positive supply for the lower gate driver.

Decouple this pin to ground with a 4.7µF or larger high-frequency ceramic

capacitor to VSS. An additional 0.1µF ceramic decoupling capacitor placed close

to VDD and VSS pin is recommended.

High-side bootstrap supply voltage for the upper gate driver referenced to HS.

Connect the bootstrap capacitor to this pin and HS.

High-side output driver. Connect to the gate of the high-side NMOS FET.

High-side gate driver reference node. Connect to the source of the high-side

NMOS FET. Connect the bootstrap capacitor to this pin and HB.

High-side driver logic input. 3.3V logic compatible and VDD tolerant.

Low-side driver logic input. 3.3V logic compatible and VDD tolerant.

VREF

Reference voltage that sets the PWM logic level thresholds. Analog supply range

of 2.7V to 5.5V. Decouple VREF to VSS with a 0.1µF ceramic capacitor. If VREF

is below 2.7V, the PWM inputs are ignored and HO = LO = 0. An internal 100kΩ

pull-down resistor places VREF in the low state when the pin is left floating.

RDT

Programmable dead time control pin. Place a resistor from the RDT pin to VSS to

set the dead time from 35ns to 350ns. The resistor range is 10kΩ to 100kΩ.

Short the RDT pin to VSS to set the dead time to 15ns. See “PCB Layout

Guidelines” on page 22 and “RDT and Dead Time Delay (HIP2210 Only)” on

page 20 for more information.

Output enable pin. When EN is low, HO = LO = 0. An internal 100kΩ pull-down

resistor places EN in the low state when the pin is left floating. Output is enabled

when EN is high (VDD tolerant).

PWM

Tri-level PWM input. Logic high drives HO high and LO low. Logic low drives HO

low and LO high. In the mid-level state, both outputs are driven low. An internal

resistor network biases the PWM pin to 50% of VREF when the pin is left floating

to set the mid-level state.

VSS

Ground reference for the VDD supply. When EPAD is available, connect VSS to

EPAD.

Low-side output driver. Connect to the gate of the low-side NMOS FET.

5, 6

No Connect. No electrical connection from this pin to the IC.

EPAD

The EPAD is electrically isolated. Connect the EPAD to the PCB ground plane

with thermal vias for heat removal. See “PCB Layout Guidelines” on page 22 for

more information.

VDD

VSS

EPAD

VDD

VREF

VSS

PWM

RDT

EPAD

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