HIP2210, HIP2211

5. Applications Information

FN9347 Rev.1.01

Page 19 of 27

Jun.23.20

dependent on the transitioning VREF voltage. The PWM open-circuit voltage is referenced to 50% of the VREF

voltage. The high impedance voltage divider resistors on the PWM pin coupled with the internal pin capacitance

form an RC circuit. During the transient turn-on and turn-off of VREF, the PWM pin open-circuit floating voltage

rises to (and falls from) 50% of VREF with an RC time constant delay relative to VREF voltage. Depending on the

dv/dt of VREF, the PWM open-circuit floating voltage can lag VREF. When PWM lags behind VREF, the PWM

comparators can see logic low on VREF turn-on (and therefore LO turns on) and see logic high on VREF turn-off

(and therefore HO turns on) until the PWM voltage falls into the mid-level logic window or VREF hits its UVLO

threshold. Although the HO/LO transitions in response to VREF ON and OFF do not violate driver operation or

produce bridge shoot through, it is not a desired transient response.

Therefore, the recommended operation of HIP2210 is to externally control the EN pin logic input such that VDD

and VREF voltages are stabilized before enabling the driver or the driver is disabled first before turning off VDD

and VREF. The VREF pin can also be tied to the bias voltage for the PWM output of the controlling MCU.

For EN = VDD applications, several options can be considered to mitigate the potential issue:

• External pull-up and pull-down resistors (such as 22kΩ) on the PWM pin to reduce the overall resistance and

the lag of the PWM voltage behind VREF

• Slower rise/fall time (1-2µs) on VREF to allow the PWM floating pin to track VREF

5.6

Selecting the Boot Capacitor Value

To provide the proper gate drive to the high-side FET, the high-side driver bias on the HIP2210 and HIP2211 is

handled with a bootstrap capacitor across the HB and HS pins. The boot capacitor is recharged whenever the HS

pin voltage goes low and forward biases the boot diode across VDD to HB. Select the boot capacitor based on the

total Qgs of the high-side NMOS FETs, switching frequency, VDD supply, and the total boot impedance, including

the dynamic resistance of the boot diode. Connect the boot capacitor close to the HIP2210/HIP2211 HB and HS

pins. A low ESL, high-frequency X7R or better ceramic capacitor is recommended.

The boot capacitor value is chosen not only to supply the internal bias current of the high-side driver but also more

significantly, to provide the gate charge of the high-side driven NMOS FET without causing the boot voltage to sag

excessively. To ensure the proper value of the bootstrap capacitor is selected, the following guideline provides

equations for calculating the boot capacitance needed.

•VDD = Driver bias charging supply

• ΔVBOOT = Maximum allowable voltage dip to ensure proper function; generally 500mV

•VHB = VDD -0.7V = VHO = Boot voltage and high-side driver bias voltage, referenced to HS

•tON = Longest on-time of the high-side; for simplicity assume the entire switching period tON = 1/ fSW

•QGS_MAX = Maximum gate charge, from NMOS FET datasheet

•IGS_LKG = Maximum NMOS FET gate-source leakage current, from NMOS FET datasheet

•RGS = Minimum gate-source discharge resistance; usually not less than 10kΩ

•IHBQ = Boot quiescent current with HI = 1 or PWM = 1

The minimum CBOOT capacitance required to ensure proper functionality becomes dependent on the total charge

required during the on state of the high side when the CBOOT is not charging, along with the allowable change in

voltage of the boot.

Equation 1 calculates the total charge required for one switching cycle of the high-side NMOS FET.

Equation 2 calculates the boot capacitor needed to support the total charge and allowable boot voltage dip

requirements:

(EQ. 1)

QTOTAL

QGS_MAX

IGS_LKG IHBQ

VHO

RGS

------------

++







tON



+

=

(EQ. 2)

CBOOT

QTOTAL

V

BOOT

------------------------

=