HIP2210, HIP2211

5. Applications Information

FN9347 Rev.1.01

Page 20 of 27

Jun.23.20

5.7

VDD Decoupling Capacitor

For VDD decoupling, Renesas recommends selecting a capacitor that is at least 10x the value of the boot

capacitor. In addition, place a low ESL, high-frequency, X7R or better ceramic capacitor of 1nF to 10nF close to

the HIP2210/HIP2211 VDD and VSS pins for high-frequency decoupling.

5.8

RDT and Dead Time Delay (HIP2210 Only)

The PWM function of the HIP2210 inherently prevents driver input shoot-through conditions by allowing only one

driver that is sourcing output to be active at one time. However, because NMOS FET gate-source capacitance

causes FET turn-on/off times to be delayed, it is necessary to have some extra dead time at the driver outputs to

prevent shoot-through conditions. The HIP2210 implements programmable dead time through the RDT pin

function.

A resistor on the RDT pin to VSS sets the HIP2210 adjustable dead time delay. The delay is between the

following:

• The falling edge of the LO output to the rising edge of the HO output

• The falling edge of the HO output to the rising edge of the LO output

The propagation delay from the PWM input to the falling edge on LO or HO is not affected by the adjustable dead

time delay circuit. For example, when PWM goes high, LO goes low from the PWM with the LO propagation delay

and HO goes high after the dead time delay set by the RDT resistor. Similarly, when PWM goes low, HO goes low

from the PWM with the HO propagation delay and LO goes high after the dead time delay set by the RDT

resistor.

The recommended resistance range on RDT pin to VSS is 10kΩ to 100kΩ, which sets a dead time delay range

typically of 35ns to 350ns. If resistance is less than 1kΩ, the adjustable dead time delay is disabled and the

nominal dead time delay on the rising edge is 15ns. Renesas recommends shorting the RDT pin to VSS to

disable the adjustable delay function. The dead time delay set by the RDT resistor is adjustable on the fly in

operation except for the disabled condition, where the disabled state is detected and latched in on POR and

resets after going through UVLO. Resistance values outside of 10kΩ to 100kΩ produce a faster or slower dead

time delay beyond the 35ns to 350ns range but the accuracy and matching performance is not guaranteed.

A 1.2V reference on the RDT pin drives a current through the RDT resistor. The current is mirrored and drives an

internal oscillator to set the dead time delay.

Note: Because the RDT pin signal is analog, as the RDT resistance is increased, the sensitivity to parasitic

capacitive and inductive pickup increases. When laying out the PCB, keep high dv/dt nodes away from the RDT

pin and resistor. Guard ringing and/or shielding can also be used to shunt away dv/dt injected currents.

5.9

HO and LO Outputs

The HO and LO driver outputs can source 3A peak and sink 4A peak currents for driving capacitive loads such as

the NMOS gate-source terminals. The strong gate drive allows low rDS(ON), high Qgs FETs to be switched on and

off quickly with minimal switching loss during the voltage and current cross-over region at the NMOS FET drain

and source.

The fast propagation delay (15ns typical) and excellent delay matching (2ns typical) supports wide duty cycle and

high-frequency applications robustly up to 1MHz.

Additionally, the LO pin has a pull-down impedance to VSS of 140kΩ and the HO pin has a pull-down impedance

to HS of 450kΩ. These internal pull-down resistors prevent charge accumulation at the external NMOS FET gate-

source capacitance that would turn on the FETs when there is no VDD bias on the HIP2210/HIP2211 driver,

preventing a possible shoot-through condition at initial power-up.

5.10 Power Dissipation

The power dissipation of the HIP2210/HIP2211 is typically dominated by the gate charge required by the driven

bridge MOSFETs and the switching frequency. The internal bias, boot diode, and MOSFET gate leakage also

contribute to the total dissipation, but these losses are usually less significant compared to the switching gate