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DSP56321RM/D bảng dữ liệu(PDF) 30 Page - NXP Semiconductors

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2-6
AC Electrical Characteristics
2.5.3
Clock Generator (CLKGEN) and Digital Phase Lock Loop
(DPLL) Characteristics
Table 2-6. CLKGEN and DPLL Characteristics
Characteristics
Symbol
220 MHz
240 MHz
Unit
Min
Max
Min
Max
Predivision factor
PDF1
116
116
—
Predivider output clock frequency range
PDFR
16
32
16
32
MHz
Total multiplication factor2
MF
5
15
5
15
—
Multiplication factor integer part
MFI1
515
515
—
Multiplication factor numerator3
MFN
0
127
0
127
—
Multiplication factor denominator
MFD
1
128
1
128
—
Double clock frequency range
DDFR
160
440
160
480
MHz
Phase lock-in time4
DPLT
6.85
1506
6.85
1506
µs
Notes:
1.
Refer to the
DSP56321 User’s Manual for a detailed description of register reset values.
2.
The total multiplication factor (MF) includes both integer and fractional parts (that is, MF = MFI +
MFN/MFD).
3.
The numerator (MFN) should be less than the denominator (MFD).
4.
DPLL lock procedure duration is specified for the case when an external clock source is supplied to the
EXTAL pin. Parameters will be refined after silicon characterization.
5.
Frequency-only Lock Mode or non-integer MF, after partial reset.
6.
Frequency and Phase Lock Mode, integer MF, after full reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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