STWBC2-HP datasheet(27/96 Pages) STMICROELECTRONICS

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Figure 31. FSK modulation circuit overview

A bit from the FIFO is drained after a programmable count of the Main PWM cycle. A cycle is completed each

time the list of events rolls over.

Note:

FW has to guarantee the non-overflow of the FSK FIFO data.

2.2.1.3.3

Chronometer

The chronometer block measures the time for which external events occurs. In a full PWM cycle, it is considered

that a positive and negative event will occur. The chronometer then stores two event times in registers.

Figure 32. Chronometer circuit overview

The external events are gated using two outputs of the signal generation block (CaptureP & N). The chronometer

tracks the count of cycles that elapsed since the start of PWM cycle. When external event occurs, the on-

going count cycles is sampled as well as the phase number at which the event appears. The phase count is

readjusted considering the phase selected at the beginning of the signal generation cycle. Then, the adjusted

timing is written into the dump registers. In addition to write data in dump registers, the Main PWM provides a

chronometer data port to be used externally. This port is connected typically to a phase demodulator. The signal

generation block can also be programmed to terminate the current step since an external event occurs. The

signal generation block can also fake an event on a defined polarity based on the timing of the other polarity.

The event list of signal generation block is copied locally so that programming of new list can be done during

PWM operation. The update of the list can be asynchronous or synchronous with the rollover of the event list

processing.

2.2.1.3.4

Enabling/Disabling

The Main PWM supports smart enabling and disabling:

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 27/96

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