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STWBC2-HP bảng dữ liệu(PDF) 74 Page - STMicroelectronics

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STWBC2-HP bảng dữ liệu(HTML) 74 Page - STMicroelectronics

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3
Electrical data
3.1
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 53 may cause permanent damage to the device.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 53. Absolute maximum ratings
Symbol
Parameter
Test condition
Min.
Max.
Unit
VIN
Power supply voltage (VIN)
-
-0.3
27
V
VDD_DRIVER
Gate driver supply voltage
(VDD_DR)
-0.3
15
V
VLSn_GD
Low-side gate driver voltage
(LS1_GD, LS2_GD, LS3_GD)
-0.3
VDR + 0.3
V
VHBn_SW
HB Switching node voltage
(HB1_SW, HB2_SW, HB3_SW)
-2
50
V
VBRG_VSNS
BRG_VSNS, DCDC_SNS
-0.3
50
V
VHBn_BT
HB Bootstrap voltage (HB1_BT,
HB2_BT, HB3_BT)
Max(VHBn_SW - 0.3
or -0.3)
Min((VHBn_SW + VDR +
0.3) or 60)
V
VHSn_GD
HB High-side gate driver voltage
(HS1_GD, HS2_GD, HS3_GD)
VHBn_SW -0.3
VHBn_BT
V
VDD
Input voltage for Analog die (VDD)
-0.3
5.5
V
VBUCK_SW
Buck switching node voltage
(BUCK_SW)
-1
27
V
VBUCK_BOOT
Buck bootstrap voltage
(BUCK_BOOT)
-0.3
32.0
V
VIN_SNS
Vin sense voltage (VIN_ISNS_P,
VIN_ISNS_M, VIN_SNS)
-0.3
Vin
V
VLDO_3V3
Input voltage for MCU die
(LDO_3V3, VREF_A, MCU_3V3)
-0.3
4
V
VIO_TT
MCU logic input voltage (I/O TT
structure pins – see
Internal signal connection
Table 38)
-0.3
4
V
VIO_FT
MCU logic input voltage (I/O FT
structure pins – see
Internal signal connection
Table 38)
-0.3
VLDO_3V3 + 4
V
VIO_DRV
General purpose driver I/Os
(GP_DRV<0:3>)
-0.3
4
V
VNRST
NRST I/O
-0.3
4
V
VLDO_1V8
Supply voltage for digital circuitry
(LDO_1V8)
-0.3
2
V
STWBC2-HP
Electrical data
DS13825 - Rev 1.0
page 74/96



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