STWBC2-HP datasheet(49/96 Pages) STMICROELECTRONICS

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The algorithm allows a pseudo steady-state operation even if the overcurrent comparator is fed with a signal low

pass filtered with 1 ms time constant.

At least at the beginning of an overcurrent condition, the charging time is updated every fixed number of cycles

(the rate is fixed by overcurrent_rate parameter). If the comparator states there is an overcurrent, the charge time

is decreased, or else the charge time is increased.

At every cycle, the discharge time is adjusted in order to stay in QR operation.

When overcurrent comparator is high and charge time is decreased, the output voltage decreases, which

reduces the current. At some point, the current is lower than the overcurrent threshold. However, any LPF in

the comparator path adds delay before having the comparator toggling low.

Hence, the charge time is decreased much more than needed.

After the charge time decreasing and the overcurrent comparator toggling low, the charge time is increased again,

enlarging the current. At some point, the current is above the threshold but the comparator is delayed because of

LPF. So, the charge time still increases before the comparator toggles high again. Hence, the current ends higher

than the limit.

Based on this fact, since the DC-DC controller has acquired these min & max charge times, it forces the charge

time to (max+min)/2 and freezes charge time variation during a programmable time (overcurrent_lock_time).

This freeze allows the LPF to converge.

When the freeze time ends, the charge time is again increased or decreased depending on the state of the

overcurrent comparator. By default, the rate of charge time modification is still fixed by the overcurrent_rate

parameter. However, if the min & max captured charge times are close together, the rate is fixed by the

overcurrent_lock_time parameter which is slower.

If the converter changes his mode (buck or boost or buck/boost), the min & max captured times are cleared which

forces a new “learning” phase for overcurrent mode.

During overcurrent mode, the buck mode is allowed only if it was on-going when the overcurrent happens.

To avoid this current oscillation directly linked with the LPF delay, the DC-DC controller stores the on-going

charging time at the time the comparator toggles low and at the time the comparator toggles high. These two

data represent the peaks of current, one being below the overcurrent threshold, the other one being above the

overcurrent threshold. So, it is very probable that a steady-state operation can happen in the middle of these two

charge times.

2.2.7.12

Short-circuit and overload

During short-circuit or overload, the DC-DC stays far away from target voltage. The DC-DC controller counts at a

slow rate the consecutive time the DC-DC stays far away from the target (the rate is dcdc_clk/8192).

If this count is above a programmable threshold, the DC-DC is stopped in error case. It can be enabled again only

if it is first disabled from the control bit.

The counter is not enabled during start-up time.

2.2.7.13

Startup

When enabled, the DC-DC controller starts with a progressive ramping of input current. The timings are updated

with the same calculation than in normal operation. However, the timings are updated at a slow rate of dcdc_clk/

8192.

In addition, a stalling time is added between each DC-DC cycle. This time begins at 241 cycle of dcdc_clk and it

is decremented by 2, 4 or 16 depending on a programmable start-up rate. This stalling time is updated at a rate of

dcdc_clk/8192.

If the output voltage reaches the target during the start-up phase, this one is cleared and the DC-DC operates

normally.

2.2.7.14

Deadtime

The DC-DC controller embeds a programmable fixed deadtime circuit.

2.2.7.15

Voltage ramp

Even if the DC-DC controller embeds a soft-start solution, this does not prevent large input current that can

happen when the regulation target voltage rises significantly. In fact, if the converter uses large output capacitor,

the converter raises its energy transfer significantly in order to charge the capacitors as fast as possible.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 49/96

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