STWBC2-HP datasheet(58/96 Pages) STMICROELECTRONICS

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Table 41. Protection operating parameters

Parameter

Value

Operating frequency

16 MHz

IO check timer

4 clock cycles

GDLS check timer

3 clock cycles

2.2.10.7

Configuration register overview

Table 42 shows the list of PROTECTION configuration registers overview.

Table 42. Protection configuration registers overview

Registers overview

Name

Description

Type

Page

Offset

Reset val.

PROT_CTRL_0

Protection control config.

R/W

0x58

0x00

PROT_CTRL_1

Protection control config.

R/W

0x59

0x00

2.2.11

NVM control logic

2.2.11.1

Overview

This block manages the control access to the embedded NVM memory.

2.2.11.2

Feature list

•

NVM deferred transaction

•

NVM single sector operation

•

NVM control enable bit to save consumption

•

NVM data order from LSB to MSB

•

NVM auto-load trimming data

•

NVM soft-program, erase and word program allowed in test mode

•

NVM clock operation configurable

2.2.11.3

Functional description

This IP manages the i/f with the NVM macro which allows read, erase and program memory command

operations.

Only a single sector operation (64-bit access) is allowed; multi-sector operation requires the iteration of the single

sector command sequences.

In functional mode the IP supports only the memory read operation while in test mode all commands are

permitted.

All memory commands are executed in a deferred way by an internal FSM controller leaving the SPI bus i/f free to

support other transactions. The memory read data are posted in the NVM_DATA_0-7 registers readable from the

SPI i/f.

Here below is shown a high level overview of the internal block diagram.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 58/96

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