STWBC2-HP datasheet(64/96 Pages) STMICROELECTRONICS

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Figure 63. DMD clock circuit overview

The clk_dmd is used in both current and voltage demodulator circuits to provide a fixed frequency closed to about

100 kHz (+/-30%). The controllability of the above circuit is done through the DEMOD_CTRL register.

The ENABLE bit controls the clock toggle functionality while the CLK_DIV represents the clock count.

The clk_out is divided by a fixed prescale value of 4-bits and is then counting the value configured in the

CLK_DIV register field from 0x01 up to 0x7F.

The CLK_DMD equation is shown in the next equation.

Fdmd= Fafe

Clkdiv* Prescale +1*2

Where:

•

Prescale = 4

•

CLK_DIV is comprised between 0x01 up to 0x7F

2.2.12.5.2

PLL clock configuration

The PLL configuration parameters require first to disable the PLL by clearing the PLL_EN bit field of register

RCC_CLK_CONFIG_1 then configures both PLL_PRE_DIV and PLL_MULT bit fields belonging to registers

RCC_CLK_CONFIG_1 and RCC_CLK_CONFIG_2, finally the PLL should be re-enabled by setting the PLL_EN

bit.

Any further register modification parameters require the iteration of the above procedures.

The RCC provides clock and reset to 16 controllable domains (peripherals). The clock source of each domain is

assigned to clk_out or pll_clk_gated[0]. Similarly, the async reset source for each domain is assigned to sync_nrst

or sync_nrst_pll_0. The configuration is static (list of define).

Table 47 shows the clock and reset signal vector assignment.

Table 47. RCC SW RST and Clock gating bit control

SW RST and Clock gating

bit

Peripheral

source

Comment

RFU

Reserved

Page 1 registers

clk_out / sync_nrst

BB-DCDC registers

Page 2 registers

clk_out / sync_nrst

HR-PWM registers

RFU

Reserved

RFU

Reserved

Page 5 registers(1)

clk_out / sync_nrst

Trimming registers, NVM and DFT registers

RFU

Reserved

clk_out / sync_nrst

Reserved

Common IPs

clk_out / sync_nrst

LEDs, ADC_MUXs, Prot, and ITC IPs

Phase demod.

clk_out / sync_nrst

Phase demodulator

RFU

Reserved

RFU

Reserved

RFU

Reserved

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

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