STWBC2-HP datasheet(21/96 Pages) STMICROELECTRONICS

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Figure 26. PLL

The PLL IP is comprised by the following main blocks:

•

Input Frequency Pre-Divider IFPD

•

Phase/Frequency Detector PFD

•

Charge Pump CPUMP

•

Loop Filter LF

•

Voltage Controlled Oscillator VCO

•

Loop Frequency Divider (in which LDF is the Loop Division Factor)

•

Delay Locked Loop DLL

Table 15. PLL operating parameters

PARAMETER/FEATURES/TOPIC

VALUE

COMMENT

Input Reference Clock Frequency (ωi)

8MHz to 56MHz

Typical 16MHz from MCU (MCO/XTAL)

Input Frequency Pre-Divider Factor – IFPD (M)

1 to 32

Adjustable

Pre-Divider Output Frequency (ωm)

2.375MHz to 20MHz

Loop Frequency Divider Factor – LDF (N)

2 to 16

Adjustable

VCO Frequency (ω0)

38MHz to 70MHz

ωo =(M/N)·ωi

Delay Locked Loop Output Frequency

38MHz to 70MHz

Frequency value of the 17 phases

(CLK<16:0>)

Maximum Lock Time

30ms + 256 cycles of PFD input

frequency

PFD frequency of 8 MHz÷20 MHz

60ms + 256 cycles of PFD input

frequency

PFD frequency of 4 MHz÷8 MHz

120ms + 256 cycles of PFD input

frequency

PFD frequency of 2.375 MHz÷4 MHz

2.1.11

GPIO

The STWBC2-HP AFE includes 4 GPIO (GPIO_DRx) that can be driven from internal PWM sources (see

Section 2.2.4 ). Using the dedicated SPI registers, these GPIO can also be used as general purpose digital input

or output.

Table 16. GPIO operating parameters

PARAMETER/FEATURES/TOPIC

VALUE

COMMENT

GPIO VDD

3.3 V

LDO3V3

STWBC2-HP

Analog AFE functions

DS13825 - Rev 1.0

page 21/96

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