ASI4U datasheet(51/71 Pages) RENESAS

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ASI4U / ASI4U-E / ASI4U-F Datasheet

January 26, 2016

4.11.2. Logic Controlled Reset

The IC is also reset after reception of Reset_Slave or Broadcast_Reset commands, expiration of the

Communication Watchdog (if enabled; see section 4.15), or entering a forbidden state machine state (i.e. due to

heavy EMI).

Important Note: If the Addressing Channel is activated and the AC Current Input Mode is selected, Reset_Slave

and Broadcast_Reset calls are processed differently than in normal operation. See corresponding explanations in

section 4.3.

4.11.3. External Reset

The IC can be reset externally by pulling the DSR pin LOW for more than a minimum reset time. The external

reset input function is provided in every operational mode of the IC: Slave Mode, Master Mode, Repeater Mode,

and Monitor Mode. The signal timings given in Table 4.25 apply to all modes.

Table 4.25 Timing of External Reset

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

DSR LOW time for no reset initiation

tnoRESET

µs

Reset execution time for DSR

HIGH/LOW transition to Hi-Z output

drives at DO0 to DO3, P0 to P3

tRESET

µs

State Machine initialization time after

reset (EEPROM read out)

tINIT

Figure 4.12 Timing Diagram External Reset via DSR

DSR

DO[3:0]

tnoRESET

P[3:0]

Hi-Z

Data port output data

Parameter port output data

Serious

Peripheral Cault

tRESET

Hi-Z

tINIT

In contrast to the A²SI, the external reset is generated “edge sensitive” to the expiration of the tRESET timer. The

initialization procedure starts immediately after the event, independent of the state of the DSR pin. A Serious

Peripheral Fault is recognized in Slave Mode if DSR remains LOW after tRESET + tINIT. The corresponding error

state display is described in section 4.9.

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