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ASI4U bảng dữ liệu(PDF) 29 Page - Renesas Technology Corp |
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ASI4U bảng dữ liệu(HTML) 29 Page - Renesas Technology Corp |
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29 / 71 page ![]() ASI4U / ASI4U-E / ASI4U-F Datasheet © 2016 Integrated Device Technology, Inc. 29 January 26, 2016 Table 4.4 IRD Current/Voltage Mode Switching PARAMETER SYMBOL CONDITIONS MIN MAX UNIT Minimum IRD input voltage to activate CMOS Input Mode of IRD pin VIRD_VM 2.5 V Maximum IRD input voltage to activate AC Current Input Mode of IRD pin VIRD_CM 1.0 V Filter time constant for IRD input mode switching tIRD_Mode_Filter 7.68 8.192 ms The following input levels apply in CMOS Input Mode: Table 4.5 IRD CMOS Input Mode Levels PARAMETER SYMBOL CONDITIONS MIN MAX UNIT Input voltage range VIRD_IN -0.3 VUout V Voltage range for input LOW level VIRD_IL 0 1.0 V Voltage range for input HIGH level VIRD_IH 2.5 VUout V Rise or fall time 1) tr or tf 100 ns 1) In Master Mode, the rise/fall time of the IRD input signal should be as low as possible in order to avoid jitter on the AS-i line. 4.3.4. Master, Repeater, and Monitor Modes In the Master, Repeater, and Monitor Modes, the IRD input is always configured in CMOS Input Mode. The input levels specified in Table 4.5 apply. The expected polarity of the Manchester-II-coded bit stream at the IRD pin depends on the values of the DI0 and DI1 pins. Table 4.6 Polarity of Manchester-II Signal at IRD in Master Mode INPUT VALUES AT DI0 AND DI1 DESCRIPTION Equal (“11” or “00”) The Manchester-II signal is active LOW (default logic output value at no communication is 1). This mode is compatible with the A²SI IRD input. Unequal (“01” or “10”) The Manchester-II signal is active HIGH (default logic output value at no communication is 0). Note: The complemented definition was chosen to retain backward compatibility to A²SI-based AS-i Master designs. |
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