HC805K3GRSSLASHD datasheet(76/119 Pages) NXP

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General Release Speciﬁcation

COP Watchdog Timer

MC68HC805K3 — Rev. 1.0

8-Bit Timer

8.4 COP Watchdog Timer

The computer operating properly (COP) watchdog timer function is

implemented on this device by using the output of the RTI circuit and

further dividing it by eight. The minimum COP reset times are listed in

Table 8-1.

If the COP circuit times out, an internal reset is generated and the reset

vector is fetched. Preventing a COP time out is done by writing a logical

zero to the COPC bit at address $03F0 as shown below. The COPR

affected by any reset signals. Reading this location returns the user

EEPROM byte. When the COPC is cleared, only the final four bits used

to count eight RTI cycles are cleared. The COP watchdog timer can be

enabled/disabled by a mask option register bit.

8.5 Operating During Stop Mode

The timer system is cleared when going into stop mode. When STOP is

exited by an external interrupt or an external RESET, the internal

oscillator resumes, followed by a 16 or 4064 cycle internal processor

oscillator stabilization delay. The timer system counter is then cleared

and operation resumes. If the STOP instruction is disabled by mask

option register bit to create the halt mode, the effects on the timer are as

described in 8.6 Operating During Wait Mode.

$03F0

Bit 7

6543

Bit 0

Read:

Reading $03F0 returns the contents of User EEPROM

Write:

COPC

Reset:

—————

—

= Unimplemented

Figure 8-4. COPR Watchdog Timer Location

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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